Enum CUDeviceAttribute
Device properties
Namespace: ManagedCuda.BasicTypes
Assembly: ManagedCuda.dll
Syntax
public enum CUDeviceAttributeFields
| Name | Description |
|---|---|
| AsyncEngineCount | Number of asynchronous engines |
| CanMapHostMemory | Device can map host memory into CUDA address space. 1 if the device can map host memory into the CUDA address space, or 0 if not |
| CanUse64BitStreamMemOps | 64-bit operations are supported in ::cuStreamBatchMemOp and related APIs. |
| CanUseHostPointerForRegisteredMem | Device can access host registered memory at the same virtual address as the CPU. |
| CanUseStreamMemOps | ::cuStreamBatchMemOp and related APIs are supported. |
| CanUseStreamWaitValueNOr | ::CU_STREAM_WAIT_VALUE_NOR is supported. |
| ClockRate | Typical clock frequency in kilohertz |
| ComputeCapabilityMajor | Major compute capability version number |
| ComputeCapabilityMinor | Minor compute capability version number |
| ComputeMode | Compute mode (See CUComputeMode for details) |
| ComputePreemptionSupported | Device supports compute preemption. |
| ConcurrentKernels | Device can possibly execute multiple kernels concurrently. 1 if the device supports executing multiple kernels within the same context simultaneously, or 0 if not. It is not guaranteed that multiple kernels will be resident on the device concurrently so this feature should not be relied upon for correctness. |
| ConcurrentManagedAccess | Device can coherently access managed memory concurrently with the CPU |
| CooperativeLaunch | Device supports launching cooperative kernels via ::cuLaunchCooperativeKernel |
| CooperativeMultiDeviceLaunch | Device can participate in cooperative kernels launched via ::cuLaunchCooperativeKernelMultiDevice |
| ECCEnabled | Device has ECC support enabled. 1 if error correction is enabled on the device, 0 if error correction is disabled or not supported by the device. |
| GlobalL1CacheSupported | Device supports caching globals in L1 |
| GlobalMemoryBusWidth | Global memory bus width in bits |
| GPUOverlap | 1 if the device can concurrently copy memory between host and device while executing a kernel, or 0 if not |
| HostNativeAtomicSupported | Link between the device and the host supports native atomic operations (this is a placeholder attribute, and is not supported on any current hardware) |
| Integrated | Device is integrated with host memory. 1 if the device is integrated with the memory subsystem, or 0 if not |
| KernelExecTimeout | Specifies whether there is a run time limit on kernels. 1 if there is a run time limit for kernels executed on the device, or 0 if not |
| L2CacheSize | Size of L2 cache in bytes |
| LocalL1CacheSupported | Device supports caching locals in L1 |
| ManagedMemory | Device can allocate managed memory on this system |
| MAX | Max elems... |
| MaxBlockDimX | Maximum block dimension X |
| MaxBlockDimY | Maximum block dimension Y |
| MaxBlockDimZ | Maximum block dimension Z |
| MaxGridDimX | Maximum grid dimension X |
| MaxGridDimY | Maximum grid dimension Y |
| MaxGridDimZ | Maximum grid dimension Z |
| MaximumSurface1DLayeredLayers | Maximum layers in a 1D layered surface |
| MaximumSurface1DLayeredWidth | Maximum 1D layered surface width |
| MaximumSurface1DWidth | Maximum 1D surface width |
| MaximumSurface2DHeight | Maximum 2D surface height |
| MaximumSurface2DLayeredHeight | Maximum 2D layered surface height |
| MaximumSurface2DLayeredLayers | Maximum layers in a 2D layered surface |
| MaximumSurface2DLayeredWidth | Maximum 2D layered surface width |
| MaximumSurface2DWidth | Maximum 2D surface width |
| MaximumSurface3DDepth | Maximum 3D surface depth |
| MaximumSurface3DHeight | Maximum 3D surface height |
| MaximumSurface3DWidth | Maximum 3D surface width |
| MaximumSurfaceCubemapLayeredLayers | Maximum layers in a cubemap layered surface |
| MaximumSurfaceCubemapLayeredWidth | Maximum cubemap layered surface width |
| MaximumSurfaceCubemapWidth | Maximum cubemap surface width |
| MaximumTexture1DLayeredLayers | Maximum layers in a 1D layered texture |
| MaximumTexture1DLayeredWidth | Maximum 1D layered texture width |
| MaximumTexture1DLinearWidth | Maximum 1D linear texture width |
| MaximumTexture1DMipmappedWidth | Maximum mipmapped 1D texture width |
| MaximumTexture1DWidth | Maximum 1D texture width |
| MaximumTexture2DArray_Height | Maximum texture array height |
| MaximumTexture2DArray_NumSlices | Maximum slices in a texture array |
| MaximumTexture2DArray_Width | Maximum texture array width |
| MaximumTexture2DHeight | Maximum 2D texture height |
| MaximumTexture2DLinearHeight | Maximum 2D linear texture height |
| MaximumTexture2DLinearPitch | Maximum 2D linear texture pitch in bytes |
| MaximumTexture2DLinearWidth | Maximum 2D linear texture width |
| MaximumTexture2DMipmappedHeight | Maximum mipmapped 2D texture height |
| MaximumTexture2DMipmappedWidth | Maximum mipmapped 2D texture width |
| MaximumTexture2DWidth | Maximum 2D texture width |
| MaximumTexture3DDepth | Maximum 3D texture depth |
| MaximumTexture3DHeight | Maximum 3D texture height |
| MaximumTexture3DWidth | Maximum 3D texture width |
| MaximumTextureCubeMapLayeredLayers | Maximum layers in a cubemap layered texture |
| MaximumTextureCubeMapLayeredWidth | Maximum cubemap layered texture width/height |
| MaximumTextureCubeMapWidth | Maximum cubemap texture width/height |
| MaxPitch | Maximum pitch in bytes allowed by the memory copy functions that involve memory regions allocated through cuMemAllocPitch_v2(ref CUdeviceptr, ref SizeT, SizeT, SizeT, UInt32) |
| MaxRegistersPerBlock | Maximum number of 32-bit registers available to a thread block; this number is shared by all thread blocks simultaneously resident on a multiprocessor |
| MaxRegistersPerMultiprocessor | Maximum number of 32-bit registers available per multiprocessor |
| MaxSharedMemoryPerBlock | Maximum amount of shared memory available to a thread block in bytes; this amount is shared by all thread blocks simultaneously resident on a multiprocessor |
| MaxSharedMemoryPerBlockOptin | Maximum optin shared memory per block |
| MaxSharedMemoryPerMultiprocessor | Maximum shared memory available per multiprocessor in bytes |
| MaxThreadsPerBlock | Maximum number of threads per block |
| MaxThreadsPerMultiProcessor | Maximum resident threads per multiprocessor |
| MemoryClockRate | Peak memory clock frequency in kilohertz |
| MultiGpuBoard | Device is on a multi-GPU board |
| MultiGpuBoardGroupID | Unique id for a group of devices on the same multi-GPU board |
| MultiProcessorCount | Number of multiprocessors on device |
| PageableMemoryAccess | Device supports coherently accessing pageable memory without calling cudaHostRegister on it |
| PCIBusID | PCI bus ID of the device |
| PCIDeviceID | PCI device ID of the device |
| PCIDomainID | PCI domain ID of the device |
| RegistersPerBlock | Deprecated, use MaxRegistersPerBlock |
| SharedMemoryPerBlock | Deprecated, use MaxSharedMemoryPerBlock |
| SingleToDoublePrecisionPerfRatio | Ratio of single precision performance (in floating-point operations per second) to double precision performance |
| StreamPrioritiesSupported | Device supports stream priorities |
| SurfaceAllignment | Alignment requirement for surfaces |
| TCCDriver | Device is using TCC driver model |
| TextureAlignment | Alignment requirement; texture base addresses aligned to textureAlign bytes do not need an offset applied to texture fetches |
| TexturePitchAlignment | Pitch alignment requirement for textures |
| TotalConstantMemory | Memory available on device for constant variables in a CUDA C kernel in bytes |
| UnifiedAddressing | Device shares a unified address space with the host |
| WarpSize | Warp size in threads |